Field of the Invention
The invention relates to chip packages and methods for forming the same, and in particular to chip packages formed by a wafer-level packaging process.
Description of the Related Art
The chip packaging process is an important step in the fabrication of an electronic product. Chip packages not only protect the chips therein from outer environmental contaminants, but they also provide electrical connection paths between electronic elements inside and those outside of the chip packages.
Manufacturing processes of chip packages comprise forming conducting layers on a substrate to electrically connect conducting pads and forming external conducting structures, such as wires or solder balls, to electrically connect the conducting layers.
However, the external conducting structures formed on the substrate increase the entire size of the chip package. As a result, it is difficult to further decrease the size of chip packages made therefrom.
Thus, there exists a need in the art for development of a chip package and methods for forming the same capable of mitigating or eliminating the aforementioned problems.